Education
-
Education:
- October 2005 to date: PhD candidate, University of Bristol “Error Tolerant Techniques for the improvement of Reliability and Yield”
- October 2004 to September 2005: MSc in Advanced Computing “Global Computing and Multimedia” - University of Bristol. Thesis Title “A Novel Soft Error Tolerant Low Power RAM Architecture”. We analyzed H-tree RAM architecture and we propose to incorporate on chip coding to protect against soft errors. It resulted in significant power savings of more than 50% and more than 34% decrease in delay over traditional RAM architecture while the reliability is significantly improved. Thesis was published in the “Proceedings of the 20th Annual Symposium on Integrated Circuits and System Design SBCCI ‘07″ ISBN:978-1-59593-816-9 page(s) 300-305.
- September 2000 to June 2004 BSc (Hons) in Computer Science and Informatics - Moscow Power Engineering Institute (Technical University) Moscow, Russia - MPEI (TU), with distinction - grade 96%. Bachelor thesis was completed in three parts:
- Programming a microcontroller to linearise the inputs of a smart transmitter.
- Create a database system for a private institute of 200 students.
- Design a computer network for two offices in 1km distance with 20PC’s.
-
Awards:
- September 2007 Scholarship for PhD Degree from Department of Computer Science against tuition fees.
- July 2007 Travel Grant award to attend conference from Research Academy of Engineering.
- August 2006 Best paper award for the paper “A Fault Tolerant Multiplier less Decimation Filter” appeared in the proceedings of International Conference on Embedded Systems, Mobile Communication and Computing, August 4th -5th 2006, Bangalore, India.
- March 2005 Scholarship for Masters Degree from Misys Foundation.
- June 2004 Top 10 students of MPEI (TU) with excellent performance.
Print This Page
Email This Page
Post a comment